| 000 -LEADER |
|---|
| fixed length control field |
02838nam a22003257a 4500 |
| 003 - CONTROL NUMBER IDENTIFIER |
|---|
| control field |
OSt |
| 005 - DATE AND TIME OF LATEST TRANSACTION |
|---|
| control field |
20250410102906.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION |
|---|
| fixed length control field |
250407b |||||||| |||| 00| 0 eng d |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER |
|---|
| International Standard Book Number |
9783031180224 [paperback] |
| 040 ## - CATALOGING SOURCE |
|---|
| Original cataloging agency |
University of Cebu-Banilad |
| Transcribing agency |
University of Cebu-Banilad |
| 100 ## - MAIN ENTRY--PERSONAL NAME |
|---|
| Personal name |
Goossens, Bernard, |
| Relator term |
author. |
| 245 ## - TITLE STATEMENT |
|---|
| Title |
Guide to computer processor architecture : |
| Remainder of title |
a RISC-V approach, with high-level synthesis / |
| Statement of responsibility, etc |
Bernard Goossens. |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. (IMPRINT) |
|---|
| Place of publication, distribution, etc |
Switzerland : |
| Name of publisher, distributor, etc |
Springer, |
| Date of publication, distribution, etc |
c2023. |
| 300 ## - PHYSICAL DESCRIPTION |
|---|
| Extent |
xxv, 438 pages : |
| Other physical details |
color illustrations ; |
| 336 ## - CONTENT TYPE |
|---|
| Source |
rdacontent |
| Content type term |
text |
| 337 ## - MEDIA TYPE |
|---|
| Source |
rdamedia |
| Media type term |
unmediated |
| 338 ## - CARRIER TYPE |
|---|
| Source |
rdacarrier |
| Carrier type |
volume |
| 504 ## - BIBLIOGRAPHY, ETC. NOTE |
|---|
| Bibliography, etc |
Includes bibliographical references and index. |
| 505 ## - FORMATTED CONTENTS NOTE |
|---|
| Formatted contents note |
Contents: Part I. Single core processors -- Part II. Multiple core processors. |
| 520 ## - SUMMARY, ETC. |
|---|
| Summary, etc |
"This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore).<br/>Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors).<br/>The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development.<br/>Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators.<br/>Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002." --Provided by the publisher |
| 521 ## - TARGET AUDIENCE NOTE |
|---|
| Target audience note |
Adult |
| 541 ## - IMMEDIATE SOURCE OF ACQUISITION NOTE |
|---|
| Deans/Chairperson |
Brigoli, Darlyne |
| Department |
College of Computer Engineering |
| Subject Category |
Computer Engineering |
| 546 ## - LANGUAGE NOTE |
|---|
| Language note |
Text in English |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Computer architecture. |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM |
|---|
| Topical term or geographic name as entry element |
Microprocessor. |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) |
|---|
| Source of classification or shelving scheme |
|
| Type of record |
Book |
| 998 ## - LOCAL CONTROL INFORMATION (RLIN) |
|---|
| Encoded by |
adryann[new] |
| Date encoded |
04/07/2025 |
| 998 ## - LOCAL CONTROL INFORMATION (RLIN) |
|---|
| Encoded by |
Janna [edited] |
| Date encoded |
04/10/2025 |
