Fundamentals of logic design / Charles H. Roth, Jr.

By: Roth, Charles HMaterial type: TextTextPublisher: Mumbia : JAICO Publishing House, c2006Edition: Fourth editionDescription: xviii, 770 pages : illustrations ; 24 cm + 1 CD-ROM (4 3/4 in.)Content type: text Media type: unmediated Carrier type: volumeISBN: 8172247745 [paperback]Subject(s): Logic circuits | Logic designDDC classification:
Contents:
Contents: 1 Introduction -- 2 Boolean algebra -- 3 Boolean algebra (continued) -- 4 Algebraic simplification -- 5 Applications of Boolean algebra -- 6 Karnaugh maps -- 7 Quine-McCluskey method -- 8 Multi-level gate networks NAND and NOR gates -- 9 Multiple-output networks, multiplexers, decoders, read-only memories, and programmable logic arrays -- 10 Combinational network design -- 11 Flip-flops -- 12 Counters and similar sequential networks -- 13 Analysis of clocked sequential networks -- 14 Derivation of state graphs and tables -- 15 Reduction of state assignment -- 16 Sequential network design -- 17 Iterative networks -- 18 MSI integrated circuits in sequential network design -- 19 Sequential network design with programmable logic devices (PLDs) -- 20 Networks for addition and subtraction -- 21 Networks for arithmetic operations -- 22 State machine design with SM charts -- 23 Analysis of asynchronous sequential networks -- 24 Derivation and reduction of primitive flow tables -- 26 Hazards -- 27 Asynchronous sequential network design
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Item type Current location Call number Status Date due Barcode
Book Book
621.395 R74 2006 (Browse shelf) Available 3UCBL000003150

Includes appendices, bibliographical references and index

Contents: 1 Introduction -- 2 Boolean algebra -- 3 Boolean algebra (continued) -- 4 Algebraic simplification -- 5 Applications of Boolean algebra -- 6 Karnaugh maps -- 7 Quine-McCluskey method -- 8 Multi-level gate networks NAND and NOR gates -- 9 Multiple-output networks, multiplexers, decoders, read-only memories, and programmable logic arrays -- 10 Combinational network design -- 11 Flip-flops -- 12 Counters and similar sequential networks -- 13 Analysis of clocked sequential networks -- 14 Derivation of state graphs and tables -- 15 Reduction of state assignment -- 16 Sequential network design -- 17 Iterative networks -- 18 MSI integrated circuits in sequential network design -- 19 Sequential network design with programmable logic devices (PLDs) -- 20 Networks for addition and subtraction -- 21 Networks for arithmetic operations -- 22 State machine design with SM charts -- 23 Analysis of asynchronous sequential networks -- 24 Derivation and reduction of primitive flow tables -- 26 Hazards -- 27 Asynchronous sequential network design

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