000			02838nam a22003257a 4500
003			OSt
005			20250410102906.0
008			250407b |||||||| |||| 00| 0 eng d
020			_a9783031180224 [paperback]
040			_aUniversity of Cebu-Banilad _cUniversity of Cebu-Banilad
100			_aGoossens, Bernard, _eauthor.
245			_aGuide to computer processor architecture : _ba RISC-V approach, with high-level synthesis / _cBernard Goossens.
260			_aSwitzerland : _bSpringer, _cc2023.
300			_axxv, 438 pages : _bcolor illustrations ;
336			_2rdacontent _atext
337			_2rdamedia _aunmediated
338			_2rdacarrier _avolume
504			_aIncludes bibliographical references and index.
505			_aContents: Part I. Single core processors -- Part II. Multiple core processors.
520			_a"This unique, accessible textbook presents a succession of implementations of the open-source RISC-V processor. Implementations are offered in increasing difficulty (non-pipelined, pipelined, deeply pipelined, multi-threaded, multicore). Each implementation is shown as a High-Level Synthesis (HLS) code in C++. This facilitates synthesis and testing on an FPGA-based development board (Such a board can be freely obtained from the Xilinx University Program targeting university professors). The book can be useful for several reasons. First, it is a novel way to introduce computer architecture: The codes given can serve as labs for a processor architecture course. Second, the book content is based on the RISC-V Instruction Set Architecture, which is an open-source machine language promising to become the main machine language to be taught, replacing DLX and MIPS. Third, all the designs are implemented through the HLS tool, which is able to translate a C program into an intellectual property (IP). Lastly, HLS will become the new standard for IP implementations, replacing Verilog/VHDL; already there are job positions tied to HLS, with the argument of rapid IP development. Hence, in addition to offering undergraduates a firm introduction, the textbook/guide can also serve engineers willing to implement processors on FPGA, as well as researchers willing to develop RISC-V based hardware simulators. Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France. He is author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002." --Provided by the publisher
521			_aAdult
541			_xBrigoli, Darlyne _yCollege of Computer Engineering _zComputer Engineering
546			_aText in English
650			_aComputer architecture.
650			_aMicroprocessor.
942			_2ddc _cBK
998			_cadryann[new] _d04/07/2025
998			_cJanna [edited] _d04/10/2025
999			_c13452 _d13452